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fifo
- 一个FIFO设计的例子，例子简单，但很经典。 是学好数字设计的好开端。-A FIFO design examples, example of simple, but very classic. Learn digital design is a good start.
fifo
- 利用一个SAM设计一个FIFO 的存储器-SAM uses a design of a FIFO memory
vhdlfi
- fifo vhdl源码，高可靠性，带有格雷码同步，有需要可依进行参考！-fifo vhdl source, high reliability, with Gray-code synchronization, there is a need-based reference!
VHDL
- 常见的输入输出及存储器件（ram及fifo）vhdl实现-The vhdl source codes of ram,fifo.
FIFO
- it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8.2i.i have tested it om my kit.[i mae my own kit for spartan2 device].you can use this code in any DSP project in which data entry is required.-it is a
connect20090223
- fpga从FIFO读数据并上传到双口ram中。-FPGA read data from the FIFO and upload it to dual-port ram Medium.
FIFO
- This code is a FIFO memory vhdl developed in ISE Software
fifo_vhdl
- FIFO的VHDL编程，其中包括FIFO的读，写，满帧，半满帧信号驱动-FIFO of the VHDL programming, including the FIFO' s read, write, full frame, half-full frame signal drive
fifodd
- 一个深度为32，字长为8_bit FIFO（先进先出）寄存器，有寄存器空、寄存器满和寄存器溢出信号。-A depth of 32, word length for 8_bit FIFO (FIFO) register, a register space, register and register full signal overflow.
fifo.vhd
- This a FIFO in VHDL Code-This is a FIFO in VHDL Code
fifo1k_32
- PCI 数据采集控制卡的内部 FIFO处理代码-Data Acquisition and Control Card PCI internal FIFO handling code
fifo_sync
- 用VHDL语言编写的FPGA程序,实现异步FIFO的功能。这个程序设计十分巧妙，精简。 -vhdl fifo sound code
VHDL
- 包括用用VHDL语言编写的DDS,FIFO,交通控制灯，数字电压计，信号发生器的源码，希望能帮到大家-Including the use of VHDL language with the DDS, FIFO, traffic control lights, digital voltage, the signal generator of the source, I hope to help you
FIFO
- 完整的FIFO完整源代码，通过仿真 完整的FIFO完整源代码，通过仿真 -Complete FIFO full source code, through the simulation of the complete FIFO full source code, through the simulation of
VHDLbasicExampleDEVELOPEMENTsoursE
- 这里收录的是《VHDL基础及经典实例开发》一书中12个大型实例的源程序。为方便读者使用，介绍如下： Chapter3：schematic和vhdl文件夹，分别是数字钟设计的原理图文件和VHDL程序； Chapter4：multiplier文件夹，串并乘法器设计程序（提示：先编译程序包）； Chapter5：sci文件夹，串行通信接口设计程序； Chapter6：watchdog文件夹，看门狗设计程序； Chapter7：taxi文件夹，出租车计价器设计程序； Chapte
fifo
- 使用Altera公司的FPGA进行VHDL开发。使用quartus2 9.0软件在EP1C3T144C8开发板上实现先进先出的队列。-The use of Altera' s FPGA-VHDL development. Use quartus2 9.0 software EP1C3T144C8 Development Board to achieve FIFO queue.
fifo
- 这个是我自己写的同步fifo ,供大家参考学习-this the syn-fifo,including testbench
FIFO.tar
- FIFO design VHDL/Verilog design
FIFO
- 先入先出FIFO，用QUARTUS进行仿真-FIFO FIFO, the simulation with QUARTUS